It is a well-known fact today that verification consumes approximately 70% of the product cycle and it is one of the main hindrance in developing a complex design. The advanced CAD tools reduces the design time but still the verification time is increasing with the design complexity. Writing directed tests for every feature of a complex design is a mind-numbing task. To alleviate this, constrained random verification is done. To check if all the design specifications are covered by these several random test cases a metric called Functional Coverage is needed. This metric gauges the progress of the verification and indicates if the destination is reached. This paper presents the development of functional coverage model for Low Power Double Data Rate 2 Memory Controller [LPDDR2 MC] in Universal Verification Methodology [UVM]. In this design there are 33 AXI v1.0 compliant masters which can write/read to/from a single memory. The LPDDR2 MC and the LPDDR2 memory model is JESD209-2F [JEDEC-standard] compliant. Hence the challenge is in identifying all the functional coverage points as per the specifications of this Design under Verification [DUV]. In this paper coverage models for AXI master interface and memory interface are implemented. 100% functional coverage was achieved when all the test cases were fired. Even after adding extra test cases functional coverage remained constant. The coverage models are reusable and thereby reduces verification time.