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International Journal of Computer Applications Technology and Research (IJCATR) call for research paper for Volume 6 Issue 2 February 2017 Edition. Submit manuscript to editor@ijcat.com. Last date of manuscript submission is January 31, 2017.

 

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International Journal of Computer Applications Technology and Research (IJCATR)

Volume 2 Issue 2 March-April 2013

A Novel Method for Encoding Data Firmness in VLSI Circuits

V. Karthikeyan, V. J. Vijayalakshmi, P. Jeyakumar

10.7753/IJCATR0202.1013

    
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Keywords:Test data volume, Test data compression, Selective encoding, Dictionary based encoding.

Abstract References BibText Highlights

       The number of tests, corresponding test data volume and test time increase with each new fabrication process technology. Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing power and time. Test data compression method can be used to solve this problem by reducing the test data volume without affecting the overall system performance. The original test data is compressed and stored in the memory. Thus, the memory size is significantly reduced. The proposed approach combines the selective encoding method and dictionary based encoding method that reduces test data volume and test application time for testing. The experiment is done on combinational benchmark circuit that designed using Tanner tool and the encoding algorithm is implemented using Model -Sim

  1. M. Abramovici, M.A. Breuer and A.D. Friedman, “Digital Systems Testing And Testable Design”, Computer Science Press, 1990
  2. N. A. Tauba, “Survey of Test Vector Compression Techniques”, IEEE Transaction Design & Test of Computers, 2006.
  3. Zhanglei Wang, Krishnendu Chakrabarty, “Test Data Compression Using Selective Encoding of Scan Slices” IEEE transactions on Very Large Scale Integration (VLSI) systems, Vol. 16, No. 11, November 2008.
  4. Usha S. Mehta, Niranjan M Devashrayee, Kanker S. Dasgupta, “Hamming Distance Based 2-D Reordering With Power Efficient Don’t Care Bit Filling Optimizing the Test Data Compression Method”, IEEE, 2010.
  5. Patrick Girard, Laboratory of Informatics, Robotics and Microelectronics of Montpellier “Survey of Low Power Testing of VLSI Circuits”, IEEE Design & Test of Computers, 2002.
  6. Witold A. Pleskacz, Tomasz Borejko, Tomasz Gugala, Pawel Pizon and Viera Stopjakova,Def Sim –The Educational Integrated Circuit for Defect Simulation, MSE’05 Anaheim, California, USA– June 12-13, 2005.
  7. K.Paramasivam, Dr.K.Gunavathi, Reordering Algorithm for Minimizing Test Power in VLSI Circuits, Engineering Letters Vol. 14, No. 1, February 2007, pp: 78-83.
  8. Lei Li , Krishnendu Chakrabarty, Nur A. Touba, “Test Data Compression Using Dictionaries with Selective Entries and Fixed- Length Indices”, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 4, October 2003, Pages 470–490.
  9. http://www.ece.uic.edu/~masud/resources.html

@article{karthikeyan02021013,
title = "A Novel Method for Encoding Data Firmness in VLSI Circuits;,
journal = "International Journal of Computer Applications Technology and Research",
volume = "2",
number = "2",
pages = "152 - 154",
year = "2013",
author = "V. Karthikeyan, V. J. Vijayalakshmi, P. Jeyakumar ",
}

Higher circuit densities in system-on-chip designs have led to drastic increase in test data volume.
Larger test data size demands not only higher memory requirements, but also an increase in testing power and time.
The proposed approach combines the selective encoding method encoding .
Method that reduces test data volume and test application time .