In integrated circuits a gargantuan portion of chip power is mostly consumed by clocking systems which comprises of flip-flops, latches and clock distribution networks. The two most widely used techniques for the reduction of dynamic and leakage power are clock gating (CG) and power gating (PG). The two techniques CG and PG are coupled in such a way that the clock enable signal is generated by CG used as sleep signal to drive the power gated cells for the reduction of leakage power. So here we first introduced bus specific clock gating (BSCG) technique which is traditional XOR based CG and it reduces the dynamic power, then the power gating (PG) technique is used for power gated cells for reduction of leakage power. All circuits are simulated in Cadence Virtuso Analog Design Environment using GPDK 45nm technology at different global clock frequencies and temperatures. The performance of proposed integrated technique is compared with power gating technique in terms of performance metrics like average power and leakage power. From simulation results, it is evident that as temperature increases both average and leakage powers is reduced and the sleepy stack technique outstands in its performance as compared with other techniques.