In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test [DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in Spartan-3e FPGA kit.