A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest clement in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In this project we design a serial –serial multiplier based on the asynchronous counter accumulation. In this serial –serial multiplier the number of sampling cycles is reduced to n from 2n by the reduction of partial products which is based on the asynchronous counters. It achieves high bit sampling rate by replacing conventional fulladder and highest 5:3 counters by simple asynchronous 1’s counters so that the critical path is limited to only AND gate and D Flip-flops.