Editor/Reviewer loginFrequency : 12 issues per year
Subject : Computer Applications and Technology
ISSN : 2319–8656 (Online)
IJCATR Volume 5 Issue 10
Pipelining Concept for Low Power DES Implementation
Ansiya Eshack S. Krishnakumar
10.7753/IJCATR0510.1005
keywords : Cryptography, DES, Fiestal Structure, FPGA, Low-power, Pipelining, Verilog
An implementation of Data Encryption Standard (DES), one of the most widely accepted cryptographic standards, using the pipelining concept is described in the paper. Pipelining is an approach used to reduce power consumption in systems. The simulation of the design employs the Xilinx software and results show that the number of slices used in the device has reduced compared to previous available works. This reduction in the slices ensures lower use of power by the system. The throughput of the system has also increased due to pipelining.
@artical{a5102016ijcatr01101005,
Title = "Pipelining Concept for Low Power DES Implementation",
Journal ="International Journal of Computer Applications Technology and Research(IJCATR)",
Volume = "5",
Issue ="10",
Pages ="654 - 656",
Year = "2016",
Authors ="Ansiya Eshack
S. Krishnakumar"}
The paper proposes a 16-stage pipelined DES structure.
The work is written using the Verilog Hardware Description Language.
Usage of pipelining in the design has increased the throughput of the system as compared to a non-pipelined system.
There is a reduction in the number of FPGA CLB Slices used by the proposed design when compared with that of previous works.