IJCATR Volume 12 Issue 3

Design of a Wide Input Voltage Low Quiescent Current LDO

Tianfu Li, Fengbo Wang, Bo Gou
10.7753/IJCATR1203.1006
keywords : LDO; wide input voltage range; low quiescent current; low-dropout linear regulator; BCD process; wide output voltage range

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A low-dropout linear regulator (LDO) with wide input voltage range, wide output voltage range and low quiescent current power consumption is proposed, which is applied to the switching power supply chip to power the internal module of the switching power supply chip. The low-dropout linear regulator is based on a P-type PowerFET design consisting of an error amplifier, a Bandgap reference. The circuit was designed and implemented by SMIC 0.18um BCD process, simulated and verified using Spectre software. The simulation results show that the linear regulation is 0.04mV/V in the input voltage range of 3.5-30V, and the load regulation is 1mV/mA in the output load current range of 10uA to 10mA, and the quiescent current is only 10uA.
@artical{t1232023ijcatr12031006,
Title = "Design of a Wide Input Voltage Low Quiescent Current LDO",
Journal ="International Journal of Computer Applications Technology and Research(IJCATR)",
Volume = "12",
Issue ="3",
Pages ="22 - 25",
Year = "2023",
Authors ="Tianfu Li, Fengbo Wang, Bo Gou"}
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