In this paper, a high-speed successive approximation analog-to-digital converter is designed based on a 40 nm CMOS process. A split-capacitor Vcm-Based switching strategy is designed, which is able to keep the output common-mode voltage constant for the DAC capacitor array without using Vcm level drive, while saving half of the capacitance compared to the conventional switching strategy and greatly reducing the area consumption. It also combines the features of binary redundancy technology and non-binary redundancy technology by splitting the highest bit capacitor to the lower bit, which enables the DAC array to generate two additional redundant bits without adding other capacitors, reducing its requirements for noise and establishment accuracy; and it adopts asynchronous timing control without external clocks, which is conducive to improving the speed of SAR ADCs and reducing the design complexity. The designed SAR ADC achieves 9.83 bit effective bits, 60.9 dB signal-to-noise distortion ratio, 77.2 dB spurious-free dynamic range, 1.68 mW overall power consumption, and 18.46 fJ/conv-step superiority at a supply voltage of 1.1 V and a sampling frequency of 100 MHz through simulation.