Editor/Reviewer loginFrequency : 12 issues per year
Subject : Computer Applications and Technology
ISSN : 2319–8656 (Online)
IJCATR Volume 12 Issue 4
Design and Implementation of an Accelerated DMA Controller based on AXI Bus
Deqing Cai, Muyao Ge, Hashi Wang
10.7753/IJCATR1204.1003
keywords : AXI bus; High bandwidth; Accelerable; DMA controller; Data verification; Low power consumption
Because Direct Memory Access (DMA) hardly consumes processor resources when carrying high-speed data, an accelerated DMA controller based on Advanced eXtensible Interface (AXI) bus protocol is proposed in this paper. The accelerable part of the controller is to replace the CPU for descriptor splitting processing by hardware, which greatly improves the CPU computing power. At the same time, the controller is equipped with eight deeply configured channels, which are used to process different types of tasks. The design supports single transmission of data and linked list transmission type, which can verify the transmitted data and ensure the security of data transmission. In this design, the working frequency of the controller can reach 500M, the power consumption is 1.3mw, and the data throughput rate can reach 40Gbps, which greatly improves the data moving efficiency of the system.
@artical{d1242023ijcatr12041003,
Title = "Design and Implementation of an Accelerated DMA Controller based on AXI Bus",
Journal ="International Journal of Computer Applications Technology and Research(IJCATR)",
Volume = "12",
Issue ="4",
Pages ="8 - 11",
Year = "2023",
Authors ="Deqing Cai, Muyao Ge, Hashi Wang"}
The accelerated controller proposed in this paper greatly improves the system performance.
The multi-channel controller designed in this paper increases the flexibility of use.
The design has the characteristics of high bandwidth and low power consumption.
The design implements hardware data verification.