Editor/Reviewer loginFrequency : 12 issues per year
Subject : Computer Applications and Technology
ISSN : 2319–8656 (Online)
IJCATR Volume 12 Issue 4
A Convolutional Neural Network Accelerator Based on FPGA
Jincheng Zou, Qing Tang, Congcong He
10.7753/IJCATR1204.1004
keywords : FPGA; Accelerator; Neural Network; Real-time; Instruction
This paper analyzes and studies the hardware programmable logic resources on small-scale FPGA chips, providing reasonable hardware resource support for subsequent neural network accelerator designs. A flexible 32-bit instruction set is designed for control by the Processing System (PS) on the Programmable Logic (PL) side, making motion state detection flexible and controllable. When designing the hardware side, this paper uses a resource-sharing strategy, and most of the calculation modules are designed using on-chip DSP resources to reduce the resource consumption of the calculation module. An innovative strategy of partially not caching the data between layers of the neural network is applied to reduce the demand for on-chip cache. To optimize on-chip storage space, this article partitions the limited BRAM space on the chip in a reasonable manner and improves the efficiency of on-chip data reading and writing through parallel processing, thereby improving the real-time performance of the neural network.
@artical{j1242023ijcatr12041004,
Title = "A Convolutional Neural Network Accelerator Based on FPGA ",
Journal ="International Journal of Computer Applications Technology and Research(IJCATR)",
Volume = "12",
Issue ="4",
Pages ="12 - 15",
Year = "2023",
Authors ="Jincheng Zou, Qing Tang, Congcong He"}
This paper employs DSPs for convolution computation in resource-limited FPGAs.
Using an on-chip BRAM multi-cache strategy has improved the bandwidth for reading data.
The design of a parallel multiplier array has improved the efficiency of computation.
The design of parallel accumulators reduces the demand for on-chip cache space.