This paper presents an architectural view of designing a digital filter. The main idea is to design a reconfigurable filter for reducing dynamic power consumption. By considering the input variation’s we reduce the order of the filter considering the coefficient are fixed. The filter is implemented using mentor graphics using TSMC .18um technology. The power consumption is decreased in the rate of 16% from the conventional model with a slight increase in area overhead. If the filter coefficients are fixed then the power can be reduced up to 18% and the area overhead can also be reduced from the reconfigurable architecture.