This paper presents a “Implementation of “Refresh And Timing Controller” unit for low power double data rate 2 memory controller (LPDDR2 MEMORY CONTROLLER). “Refresh and Timing Controller” unit plays a vital role for LPDDR2 memory controller .It maintains different timing parameters to handle various commands for memory like refresh, read and write operations and also performs Memory Initialization. Since it is low power DDR2 the maximum duration in power-down mode and deep power down mode is maintained by “Refresh and Timing Controller” unit. The refresh rate period is programmable using the Refresh Period Register. It supports “All Bank Refresh”. The unit has timers to accommodate Refresh, Read/Write, and Power down modes. The RTL is done using the System Verilog. The design is simulated