The Phase Frequency Detectors (PFD’s) are proposed in this research paper by using the two different structures of D Flip-Flop that is the traditional D Flip-Flop and modified D Flip-Flop with a NAND gate which can overcome the speed and area limitations of the conventional PFD. Both of the PFD’s use 20 transistors. The traditional PFD consumes 133.92 ?W power when operating at 40 MHz frequency with 1.8 Volts supply voltage whereas the modified PFD consumes 100.51 ?W power operating at 40 MHz frequency with 1.8 Volts supply voltage. The designs are implemented by using 0.18 meter CMOS process in Tanner 13.ov. These can be used in PLL for high speed applications.